The present invention relates generally to analog to digital converters, and more specifically, to a delta-sigma modulation analog to digital converter with increased resolution and stability.
Two basic techniques for implementing an analog-to-digital converter (ADC) are the open-loop technique and the feedback technique. An open-loop converter generates a digital code directly upon application of an input voltage and is generally asynchronous in operation. A feedback converter generates a sequence of digital codes from an input signal, reconverts the digital codes to an analog signal and feeds back the analog signal.
A typical first-order sigma-delta ADC is shown in FIG. 1 as 100. An analog signal received at an input 102 is applied to a subtracting circuit 104, where a feedback signal (to be described later) is subtracted from the analog signal received at the input. The resulting signal is integrated in an integrator, and the resulting integrated output is applied to a quantizer 108 to produce a digital number representing a level of the integrated output. The digital number output by the quantizer 108 is applied to a digital-to-analog converter (DAC) 110 to provide the feedback signal noted above. The digital number output by the quantizer 108 is also applied to a digital FIR filter 112, where it is low-pass-filtered, and to a downsampler 114, where it is downsampled. The resulting digital signal is output at an output 116.
Within the context of ADC""s based on the sigma-delta architecture there are three basic approaches to increase the resolution: 1) Increase the oversampling ratio, 2) Increase the order of the modulator, 3) Increase the quantizer resolution. Those approaches have led to improvements of ADC resolution throughout the last decade; however, designs based upon those principles have been optimized, and further improvements will likely be modest. The prior art has concentrated mostly on employing band-pass filters in the modulator. However, a band-pass approach reduces the slope of the SNR increase versus modulator order by a factor of two. Therefore, such designs incur additional complication and concomitant performance penalties.
The following three U.S. patents are believed to be the most relevant to the subject matter of the present application.
U.S. Pat. No. 5,027,120, xe2x80x9cDelta-sigma converter with bandpass filter for noise reduction xe2x80x9d
Analogue signals are converted to digital data by use of a Sigma-Delta modulator including a pair of bandpass filters and a feedback loop including a digital to analogue converter. The tendency of such a circuit to instability is reduced or eliminated by making small variations in the phase of a clock controlling feedback pulses relative to a clock controlling data output pulses. As an alternative, corrections may be made to the feedback pulses by an additional feedback loop providing pulses for correcting the feedback pulses. That patent covers the idea of bandpass signal conversion technique and its instability reduction.
U.S. Pat. No. 5,179,380, xe2x80x9cOne-bit sigma-delta modulator with improved signal stabilityxe2x80x9d
The one-bit sigma-delta modulator with improved signal stability disclosed includes, in order, a first anti-aliasing filter, a chopper, a second anti-aliasing filter, and a one-bit modulator. The chopper and one-bit modulator are driven by a clock generator. The chopper is introduced to provide a carrier upon which the signal may ride, thereby eliminating dc stability problems. The first anti-aliasing filter eliminates aliasing from the chopper, and the second anti-aliasing filter eliminates aliasing from the one-bit modulator. The second anti-aliasing filter may be eliminated if the frequency of the chopper is an exact integer submultiple of the sampling frequency of the one-bit modulator. This invention may drive a decimation filter, to provide a low cost analog-to-digital converter.
That patent covers the general idea of an input signal modulation in order to decrease instability problems caused by a DC offset. It specifically limits itself to a one-bit modulator and does not cover multi-bit sigma-delta modulators and their stability issues.
U.S. Pat. No. 5,442,353, xe2x80x9cBandpass sigma-delta analog-to-digital converter (ADC), method therefor, and receiver using samexe2x80x9d
A bandpass sigma-delta analog-to-digital converter (ADC) (10) includes first (11) and second (12) band pass sigma-delta modulators, and a digital filter (13) connected to digital outputs thereof. In the illustrated embodiment, the first band pass sigma-delta modulator (11) is a second-order, single bit bandpass modulator, and the second bandpass sigma-delta modulator (12) is a first-order, multiple-bit modulator. Coefficients in feedback paths of the first (1) and second (12) modulators are derived from a transfer function of the digital filter. In one embodiment, a receiver (50) for a system such as frequency modulation (FM) radio converts an intermediate frequency (IF) analog signal to digital in-phase (I) and quaternary (Q) signals using the bandpass sigma-delta ADC (10). That patent covers only the idea of bandpass signal conversion technique, and its instability reduction.
U.S. Pat. No. 4,994,804 xe2x80x9cDouble integration delta-sigma modulation analog to digital converterxe2x80x9d
The abstarct of that patent states xe2x80x9cA delta-sigma modulation analog to digital converter for converting an analog input signal to a digital output signal. The converter includes an input circuit for receiving the analog input signal, a clock generator for generating a very high frequency clock signal with first and second phases, a first switching circuit coupled to the input circuit for modulating the analog input signal with the very high frequency clock signal, an integration circuit coupled to the first switching circuit for integrating the modulated input signal and generating a noise signal, a second switching circuit coupled to the integration circuit both for demodulating the integrated modulated input signal and modulating the noise signal with the very high frequency clock signal, a quantizing circuit coupled to the second switching circuit for responsive to the demodulated input signal and the modulated noise signal for generating the digital output signal including a separable portion corresponding to the modulated noise signal and a feedback circuit coupled between the quantizing circuit and the integration circuit both for generating a feedback signal corresponding to the digital output signal and feeding the feedback signal to the integration circuit.xe2x80x9d
That patent covers the idea of modulating an input signal with a very high frequency clock signal similar to the method of the present invention. However, the referenced patent employs a conventional integrator as the modulator filter which, by consequence, fails to achieve the favorable noise shaping properties of the present invention.
It will be apparent from the above that a need exists in the art to improve the resolution of the sigma-delta ADC without reducing performance or increasing complexity to the degree experienced in the prior art. It is therefore an object of the present invention to provide an architecture to do so.
To achieve the above and other objects, the present invention uses a xe2x80x9cMirrored Integratorxe2x80x9d (MI) in the modulator. The modulator itself could be of the N-th order and it could employ an M-bit quantizer and M-bit Digital-to-analog converter (DAC). The new approach retains the low-pass sigma-delta slope of the SNR. In addition, the noise-shaping property of the sigma-delta converter employing a MI is that the quantization noise is shaped toward the low-frequency portion of the spectrum (in opposition to conventional Sigma-delta converters where the quantization noise is shaped toward the high-frequency portion of the spectrum). In the new approach, the output signal may be passed through a high-pass filter (in opposition to a conventional sigma-delta converter in which the signal is passed through a low-pass filter). After filtering, in order to shift the signal back to the low-frequency portion of the spectrum, the signal may be decimated by employing the procedure used in conventional Sigma-delta converters. In an ideal situation, where analog noise is flat over the spectrum, and where both the quantizer and DAC are ideal, there is no improvement offered by the new design. However, in practice, 1/f noise in the modulator is dominant at frequencies extending up to 500 kHz, and DAC non-linearity as well as nonlinearities introduced by the opamp and quantizer output limits are always evident in the lower portion of the spectrum regardless of the input signal frequency. Therefore, the noise-shaping property of the new architecture, in which the noise is xe2x80x9cpushedxe2x80x9d toward the low-frequency portion of the spectrum, which is already cluttered with the 1/f noise and DAC and/or quantizer harmonic distortion, and then filtered out by the high-pass filter affords an overall improvement in resolution over the conventional sigma delta ADC design.
An important aspect of the new approach is based upon shifting the input signal to the upper frequency range of the spectrum. In the new approach described here, the input signal is frequency-shifted into the upper-most part of the spectrum. Specifically, the frequency spectrum of the input signal is shifted up to near the Nyquist frequency (which is defined as one-half of the sampling frequency and which equals the bandwidth of the ADC).
It will be readily apparent that the modulator or converter according to the present invention can be, but is not necessarily, implemented in a single chip. Other implementations could be developed, such as discrete components, implementation in a programmable computing device through appropriate software, or optical computing.